1. Field of the Invention
The present application relates to an array substrate for a display device, and more particularly, to an array substrate including a thin film transistor that has a channel region of polycrystalline silicon and a method of fabricating the array substrate.
2. Discussion of the Related Art
As information age progresses, flat panel display (FPD) devices having light weight, thin profile, and low power consumption have been substituted for cathode ray tube (CRT) devices. Liquid crystal display (LCD) devices, plasma display panel (PDP) devices, field emission display (FED) devices, and electroluminescent display (ELD) devices are examples of the FPD devices. Since the LCD device including thin film transistors as a switching element that controls an applied voltage to each pixel, referred to as an active matrix LCD (AM-LCD) device, has excellent characteristics of high resolution and displaying moving images, the AM-LCD device has been widely used.
In addition, the ELD devices using an organic emitting material, referred to as organic electroluminescent display (OELD) devices, display images with relatively high brightness and low drive voltages. Since the OELD devices have an emissive type, the OELD devices have a preferred contrast ratio with an ultra slim profile. Additionally, the can easily display moving images because they have a short response time of only several microseconds. Moreover, the OELD devices have no limitation in viewing angle and stably operate even at relatively low temperatures. Furthermore, since the OELD devices operates with only a low voltage, for example, about 5V to 15V DC (direct current), driving circuits for the OELD devices can be cheaply and easily fabricated. Accordingly, the OELD devices have been the subject of recent research and development.
Each of the LCD devices and the OELD devices includes an array substrate having a thin film transistor (TFT) as a switching element that controls an applied voltage to each pixel. Accordingly, the TFT in each pixel region is connected to a gate line, a data line and a pixel electrode to transmit a data signal of the data line to the pixel electrode according to a gate signal of the gate line.
FIG. 1 is a cross-sectional view showing a thin film transistor having a semiconductor layer of amorphous silicon for an array substrate according to the related art. In FIG. 1, a gate electrode 10 is formed on a substrate 9 in a transistor area TrA of a pixel region P and a gate insulating layer 18 is formed on the gate electrode 10. A semiconductor layer 20 including an active layer 20a of intrinsic amorphous silicon and an ohmic contact layer 20b of impurity-doped amorphous silicon is formed on the gate insulating layer 18 over the gate electrode 10. The ohmic contact layer 20b on end portions of the active layer 20a is spaced apart from each other to expose a central portion of the active layer 20a. Source and drain electrodes 26 and 28 are formed on the ohmic contact layer 20b to expose the central portion of the active layer 20a. The gate electrode 10, the gate insulating layer 18, the semiconductor layer 20, the source electrode 26 and the drain electrode 28 constitute a thin film transistor (TFT) Tr.
A passivation layer 36 is formed on the TFT Tr and has a drain contact hole 30 exposing the drain electrode 28. A pixel electrode 38 is formed on the passivation layer 36 and is connected to the drain electrode 28 through the drain contact hole 30. Although not shown in FIG. 1, a gate line connected to the gate electrode 10 and a data line connected to the source electrode 26 are formed over the substrate 9.
In the array substrate according to the related art, the active layer 20a of the TFT Tr includes amorphous silicon. Since the amorphous silicon has a random atomic arrangement, the amorphous silicon has a quasi-static state when a light is irradiated or when an electric field is applied. As a result, the TFT having the active layer 20a of amorphous silicon has a disadvantage in stability. In addition, since carriers in a channel region of the active layer 20a of amorphous silicon have a relatively low mobility within a range of about 0.1 cm2/Vsec to about 1.0 cm2/Vsec, the TFT having the active layer 20a of amorphous silicon has a disadvantage in usage for a switching element of a driving circuit.
To solve the above problems of amorphous silicon, a TFT having an active layer of polycrystalline silicon and a method of fabricating the TFT by crystallizing amorphous silicon to form polycrystalline silicon have been suggested. For example, amorphous silicon of the active layer may be crystallized by an excimer laser annealing (ELA) process to become polycrystalline silicon.
FIG. 2 is a cross-sectional view showing a thin film transistor having a semiconductor layer of polycrystalline silicon for an array substrate according to the related art. In FIG. 2, a buffer layer 53 is formed on a substrate 51 and a semiconductor layer 55 including a channel region 55a, a source region 55b and a drain region 55c is formed on the buffer layer 53. The channel region 55a includes intrinsic polycrystalline silicon and the source and drain regions 55b and 55c at both sides of the channel region 55a includes impurity-doped polycrystalline silicon. For example, the source and drain regions 55b and 55c may be doped with positive impurities of high concentration (p+) or negative impurities of high concentration (n+). A gate insulating layer 58 is formed on the semiconductor layer 55 and a gate electrode 59 is formed on the gate insulating layer 58 over the semiconductor layer 55. An interlayer insulating layer 61 is formed on the gate electrode 59. The gate insulating layer 58 and the interlayer insulating layer 61 includes first and second contact holes 63 and 64 exposing the source and drain regions 55b and 55c, respectively.
In addition, source and drain electrodes 70 and 72 are formed on the interlayer insulating layer 61. The source and drain electrodes 70 and 72 are connected to the source and drain regions 55b and 55c through the first and second contact holes 63 and 64, respectively. The semiconductor layer 55, the gate insulating layer 58, the gate electrode 59, the source electrode 70 and the drain electrode 72 constitute a thin film transistor (TFT) Tr. A passivation layer 75 is formed on the source and drain electrodes 70 and 72, and a pixel electrode 82 is formed on the passivation layer 75. The passivation layer 75 includes a third contact hole 78 exposing the drain electrode 72 and the pixel electrode 82 is connected to the drain electrode 72 through the third contact hole 78.
The source and drain regions 55b and 55c may be doped with impurities using a doping apparatus. As a result, an additional apparatus is required for the TFT Tr having the semiconductor layer 55 of polycrystalline silicon and fabrication cost increases. Further, since the TFT Tr having the semiconductor layer 55 of polycrystalline silicon has a complicated structure as compared with the TFT Tr (of FIG. 1) having a semiconductor layer 20 (of FIG. 1) of amorphous silicon, production yield is reduced.
Moreover, the semiconductor layer 55 of polycrystalline silicon may be obtained by an excimer laser annealing (ELA) process using an excimer laser apparatus. The excimer laser apparatus emits pulsed rays having a wavelength of about 308 nm using a gas of xenon chloride (XeCl). Since the pulsed rays of the excimer laser apparatus have a relatively great fluctuation in energy density, the semiconductor layer 55 has different crystallinities according to positions. As a result, the TFT Tr has non-uniform characteristics according to positions and display quality of a display device having the TFT Tr is deteriorated by a striped stain due to the non-uniformity in characteristics of the TFT Tr.
As compared with an array substrate for an LCD device driven by a voltage, specifically, an array substrate for an OELD device is driven by a current. Accordingly, a grey level of an image is controlled by a current flowing through a driving transistor in an array substrate for an OELD device. As a result, the non-uniformity in characteristics of the TFT Tr having a semiconductor layer 55 of polycrystalline silicon further deteriorates display quality in an array substrate for an OELD device.
Therefore, the TFT having a semiconductor layer of amorphous silicon has disadvantages in stability and mobility, and the TFT having a semiconductor layer of polycrystalline silicon has disadvantages in uniformity and productivity.